Hardware research and materials for Transformer model implementations
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This repository serves as a curated collection of research papers and materials focused on the hardware implementation of Transformer models, particularly BERT. It targets researchers and engineers interested in optimizing Transformer architectures for efficient execution on specialized hardware like FPGAs and ASICs. The primary benefit is a comprehensive overview of the evolving landscape of hardware-algorithm co-design for Transformer acceleration.
How It Works
The repository organizes research papers chronologically and by topic, highlighting advancements in areas such as model compression (quantization, pruning), novel accelerator architectures (FPGA, ReRAM, PIM), and algorithm-hardware co-optimization. It showcases how researchers are tackling the computational and memory demands of Transformers to enable their deployment on resource-constrained edge devices or to improve performance on larger systems.
Quick Start & Requirements
data/papers.yaml
.Highlighted Details
Maintenance & Community
Licensing & Compatibility
Limitations & Caveats
This repository is a collection of research pointers and does not provide executable code or implementations. The "quick start" is for contributing to the list, not for running any accelerated models. Users must independently access and evaluate the referenced research papers.
5 months ago
Inactive