xilinx-skill  by QingquanYao

AI drives end-to-end FPGA and MPSoC design

Created 1 month ago
257 stars

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Project Summary

This repository offers an AI-powered "skill" for Claude Code, OpenAI Codex, and OpenClaw, designed to automate the Xilinx/AMD FPGA and MPSoC design workflow. It translates natural language requirements into executable Tcl scripts for Vivado, Vitis HLS, Vitis Unified, and PetaLinux, enabling users to focus on architecture design rather than complex scripting. The skill covers the full design flow from HLS IP generation to bootable images, significantly streamlining development.

How It Works

The skill integrates with AI assistants to interpret natural language design needs, generating scripts for the entire Xilinx toolchain. A key feature is the optional MCP Server suite, enabling AI agents direct control over Xilinx tools and infrastructure for fully automated debugging and development. This approach abstracts complex Tcl APIs, cross-toolchain data flows, and common pain points like version compatibility and constraint syntax.

Quick Start & Requirements

Installation varies: Claude Code uses /plugin marketplace add QingquanYao/xilinx-skill then /plugin install xilinx-suite. Codex/OpenClaw require cloning the repo and running an install script (install.sh or install.ps1). Prerequisites include the chosen AI assistant, Xilinx Vivado, Vitis HLS, Vitis Unified IDE (2022.x+), and PetaLinux. Full automation requires installing MCP Servers (vivado-mcp, vitis_mcp, etc.).

Highlighted Details

  • Automates Vivado Tcl scripting, PS configuration, and XDC constraint generation from natural language.
  • Manages the HLS IP -> Vivado -> XSA -> Vitis/PetaLinux data flow.
  • Provides a step-by-step guide for JESD204B to JESD204C migration.
  • Features a comprehensive reference documentation library covering the Xilinx toolchain.
  • Outputs are structured by design stage (HLS, Vivado, Vitis, PetaLinux).

Maintenance & Community

Community-maintained, with contributions welcomed for documentation, API details, and error correction. See CONTRIBUTING.md.

Licensing & Compatibility

Released under the permissive MIT license, suitable for commercial use and closed-source linking.

Limitations & Caveats

Full automation relies on installing and configuring Xilinx toolchains (e.g., Vitis Unified 2022.x+) and the optional MCP Server suite. The primary README is in Chinese, though English documentation links are available.

Health Check
Last Commit

3 weeks ago

Responsiveness

Inactive

Pull Requests (30d)
0
Issues (30d)
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Star History
83 stars in the last 30 days

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