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QingquanYaoAI drives end-to-end FPGA and MPSoC design
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This repository offers an AI-powered "skill" for Claude Code, OpenAI Codex, and OpenClaw, designed to automate the Xilinx/AMD FPGA and MPSoC design workflow. It translates natural language requirements into executable Tcl scripts for Vivado, Vitis HLS, Vitis Unified, and PetaLinux, enabling users to focus on architecture design rather than complex scripting. The skill covers the full design flow from HLS IP generation to bootable images, significantly streamlining development.
How It Works
The skill integrates with AI assistants to interpret natural language design needs, generating scripts for the entire Xilinx toolchain. A key feature is the optional MCP Server suite, enabling AI agents direct control over Xilinx tools and infrastructure for fully automated debugging and development. This approach abstracts complex Tcl APIs, cross-toolchain data flows, and common pain points like version compatibility and constraint syntax.
Quick Start & Requirements
Installation varies: Claude Code uses /plugin marketplace add QingquanYao/xilinx-skill then /plugin install xilinx-suite. Codex/OpenClaw require cloning the repo and running an install script (install.sh or install.ps1). Prerequisites include the chosen AI assistant, Xilinx Vivado, Vitis HLS, Vitis Unified IDE (2022.x+), and PetaLinux. Full automation requires installing MCP Servers (vivado-mcp, vitis_mcp, etc.).
Highlighted Details
Maintenance & Community
Community-maintained, with contributions welcomed for documentation, API details, and error correction. See CONTRIBUTING.md.
Licensing & Compatibility
Released under the permissive MIT license, suitable for commercial use and closed-source linking.
Limitations & Caveats
Full automation relies on installing and configuring Xilinx toolchains (e.g., Vitis Unified 2022.x+) and the optional MCP Server suite. The primary README is in Chinese, though English documentation links are available.
3 weeks ago
Inactive