Summary

Ztachip offers an open-source hardware/software platform for edge AI deployment on low-power FPGAs or custom ASICs. It provides a RISC-V based accelerator delivering significant speedups for vision and AI tasks, targeting engineers building embedded intelligent systems.

How It Works

The platform integrates a VexRiscv CPU with a custom "ztachip" accelerator. This accelerator features a scheduler, dataplane, and a novel Tensor Engine. The Tensor Engine, composed of 28 configurable Pcores, can act as a systolic array for in-memory compute, accelerating diverse tasks from vision processing to AI models, unlike accelerators limited to specific operations. A C-like DSL compiler generates instructions for the tensor processor, enabling massive data parallelism.

Quick Start & Requirements

Setup requires cloning the repo, building a RISC-V GNU toolchain (rv32im, ilp32), and installing Ubuntu prerequisites (e.g., autoconf, automake, python3-pip, numpy). Detailed build procedures exist for C/C++, MicroPython, and LLM chatbot demos. FPGA synthesis needs Xilinx Vivado Webpack. Demos are shown on an ArtyA7-100T board, with reference designs requiring additional camera/VGA modules. Documentation is available within the repo.

Highlighted Details

• Achieves 20-50x acceleration for AI/vision tasks over non-accelerated RISC-V, outperforming vector extensions.
• The Tensor Engine's flexibility supports diverse applications beyond typical CNN workloads.
• Offers both a C-like DSL compiler and a MicroPython port for programming flexibility.
• Includes pre-built acceleration libraries for common vision and AI functions.

Maintenance & Community

Support is available via GitHub issues/discussions. Business consulting and support are also offered.

Licensing & Compatibility

A LICENSE.md file is present, but the specific license terms are not detailed in the README. The platform is designed for FPGA or custom ASIC deployment.

Limitations & Caveats

The build process, especially for the RISC-V toolchain, is lengthy. Running demos requires specific hardware (ArtyA7-100T, potentially camera/VGA modules). Porting to different platforms necessitates implementing specific hardware wrapper layers.