This repository serves as a comprehensive, curated list of resources exploring the integration of Large Language Models (LLMs) into Electronic Design Automation (EDA). It targets researchers, engineers, and practitioners seeking to leverage LLMs for tasks ranging from hardware description language (HDL) generation and verification to complex design optimization and natural language interaction with EDA tools. The primary benefit is a centralized overview of emerging techniques, datasets, and benchmarks, accelerating adoption and innovation in AI-driven EDA.

How It Works

The collection highlights diverse approaches applying LLMs to EDA challenges. Key themes include LLMs as autonomous agents capable of task planning and tool execution for iterative design refinement, domain-specific LLMs fine-tuned on EDA corpora (like ChipNeMo), and multimodal models (Large Circuit Models) that harmonize various data sources (specifications, netlists, layouts). These methods aim to automate complex design flows, improve code generation quality (RTL, scripts, assertions), enhance verification processes, and enable more intuitive human-computer interaction paradigms for EDA software.

Quick Start & Requirements

This repository is a curated list of research papers and projects, not a single installable software package. Specific project requirements (e.g., GPU, CUDA, Python versions, datasets) vary by the individual resource listed. Interested users should refer to the respective project links within the README for detailed setup instructions. The primary resource linked is the arXiv preprint for the "LLM4EDA" paper: https://arxiv.org/abs/2401.12224.

Highlighted Details

• Covers LLM applications in RTL generation, HDL/script generation, code analysis (bug detection, security), formal verification, testbench generation, and analog circuit design.
• Features projects like ChipNeMo (domain-adapted LLMs for chip design), ChatEDA (autonomous EDA agent), RapidGPT (HDL pair-designer), and Large Circuit Models (multimodal circuit representation).
• Addresses the critical challenge of evaluating LLM-generated code quality, including syntax correctness, functional equivalence, PPA (Power, Performance, Area), and security.
• Explores LLMs as agents for task planning and tool execution in chip design workflows.

Maintenance & Community

The list is maintained by members of SJTU-Thinklab. The primary citation provided is for the paper "LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation" (arXiv:2401.12224). No direct community links (e.g., Discord, Slack) or specific contributor details beyond the maintaining lab are provided in the README.

Licensing & Compatibility

The README does not specify a software license for the curated list itself, nor does it detail the licenses of the individual projects referenced. Users must consult the original sources for licensing information and compatibility, particularly concerning commercial use or integration into closed-source systems.

Limitations & Caveats

The field is described as "emerging," indicating ongoing research and development. Many listed projects focus on evaluation, benchmarks, and foundational research, suggesting that robust, production-ready tools may be limited. Challenges remain in evaluating the quality, security, and PPA of LLM-generated designs, and the practical deployment of LLM agents in complex EDA flows is still an active area of investigation.